Flash memory is a type of semiconductor computer memory with many desirable characteristics. Like read only memory, ROM, it is non-volatile, meaning that the contents of the memory are stable and retained without applied electrical power.
Flash memory devices have found wide commercial success in the electronic device market. A major advantage of flash over ROM is that the memory contents of flash may be changed after the device is manufactured. Flash memory has found wide acceptance in many types of computers, including desktop computers, mobile phones and hand held computers. Flash memory is also widely used in digital cameras and portable digital music players, for example “MP3” players.
In addition to direct flash storage applications, for example in video cameras, flash-based storage devices are replacing rotating magnetic disks, sometimes known as hard drives, in many applications. Compared to hard drives, flash is significantly more rugged, quieter, lower power, and for some densities such a flash based device may be smaller than a comparable hard drive.
FIG. 1 shows a memory cell 10 as has been well known in the conventional art. Regions 14 are the drain and/or source regions for memory cell 10. They may be used as source and/or drain interchangeably. Control gate 16 is used to control the operation of memory cell 10. A channel region 17 is formed between source/drain regions 14. Feature size 18 is the nominal size of the smallest feature that can be created by a particular semiconductor process. In memory cells of this type, the gate 16 width and channel 17 length typically correspond approximately to feature size 18.
Memory cell 10 may be one of two general types of non-volatile memory, a “floating gate” cell or a nitride read only memory (NROM) cell. In a floating gate cell, layer 12B of the gate stack is typically conductive polysilicon. Layers 12A and 12C are insulating materials which isolate or “float” gate layer 12B, which is usually referred to as a floating gate. Floating gate 12B is the storage element of memory cell 10.
Silicon nitride based flash memory has many advantages as compared to its floating gate and tunneling oxide based counterparts. Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) is potentially very dense in terms of number of cells per unit area that can be used and it requires fewer process steps as compared to floating gate memory. Moreover, it can be easily integrated with standard SRAM process technology. A further advantage of using SONOS devices is their suitability for applications requiring large temperature variations and radiation hardening. The SONOS stack is a gate dielectric stack and consists of a single layer of polysilicon, a triple stack ONO (Oxide-Nitride-Oxide) gate dielectric layer and a MOS channel 17. The ONO structure may consist of a tunnel oxide 12A, a nitride memory storage layer 12B and a blocking oxide layer 12C.
Flash memory devices are typically configured as an array of many instanced of individual cells, e.g., cell 10, oriented in rows and columns. Typically, the control gates, e.g., control gate 16 of FIG. 1, of the cells in each row are connected to a series of word lines, thus forming individual rows of cells that can be accessed by selecting the corresponding word line. Similarly, the source and/or drain, e.g., regions 14, of the cells in each column are connected to a series of bit lines, thus forming individual columns of cells that can be accessed by selecting the corresponding bit lines.
Memory device manufacturers are continually challenged to provide ever greater amounts of memory at ever lower costs. Recently, Advanced Micro Devices, Incorporated of California has introduced MIRROR BIT™ nitride-based flash ROM that stores multiple bits per memory cell 10 physically separated in nitride layer 12B. Such storage of multiple bits per cell increases the storage density of the memory device, thereby reducing the cost per bit of storage.
To read a bit stored in the “left” portion of memory cell 10, a word line is brought to a read voltage of about 4.5 volts and a bit line is grounded. Node 14A (the “left” instance of regions 14) functions as a source for the cell, and current flows from node 14B, acting as a drain, to node 14A through a bit line to ground. Sensing logic connected to the bit line can interpret the magnitude of the current (which is affected by the amount of charge stored in nitride gate layer 12B) in order to determine if a bit is stored in the “left” portion of cell 10.
To read a bit stored in the “right” portion of memory cell 10, a word line is brought to a read voltage of about 4.5 volts and a bit line is grounded. Node 14B (the “right” instance of regions 14) functions as a source for the cell, and current flows from node 14A, acting as a drain, to node 14B through a bit line to ground. Sensing logic connected to the bit line can interpret the magnitude of the current (which is affected by the amount of charge stored in nitride gate layer 12B) in order to determine if a bit is stored in the “right” portion of cell 10.
To write (or program) a bit into the “right” portion of memory cell 10, a line is brought to a programming voltage of about 9.5 volts, and a bit line is grounded and acts as a source. Current is sourced from the word line through node 14A into bit line. The current causes hot carrier injection of charge into the nitride layer of the SONOS stack in physical proximity to node 14A.
To write (or program) a bit into the “left” portion of memory cell 10, a line is brought to a programming voltage of about 9.5 volts, and a bit line is grounded and acts as a source. Current is sourced from the word line through node 14B into bit line. The current causes hot carrier injection of charge into the nitride layer of the SONOS stack in physical proximity to node 14B.
Most low power flash memory devices operate, e.g., read and program, on a single external voltage supply, for example 1.8 volts. Internal voltages, e.g., a bias voltage of 9.5 volts for programming or a bias voltage of 4.5 volts for reading, are typically generated by auxiliary circuits, for example, a charge pump, on a flash memory integrated circuit. There are many advantages realized by product designers (e.g., a designer using flash memory in a product) from a single-supply part such as a flash memory. For example, a product designer only needs to design a single power supply for a product. Efficient product-level power supplies frequently require magnetic devices, e.g., inductors. Inductors frequently are rather “tall” components. Limiting the number of “tall” components beneficially allows for thinner products. As a further benefit, a single-supply device isolates a product designer from the details of device voltage requirements. A device designer is better able to beneficially select operating voltage(s) for optimum performance.
In addition, an integrated circuit implementation of a power conversion circuit may typically be smaller and less expensive than a system-level circuit board implementation. A further advantage of integrating power conversion circuitry into a single-supply integrated circuit is related to “second sourcing” of components. Many manufacturers of high volume electronic assemblies require similar components to be available from at least two (a first and a “second”) independent supply chains. In the case of flash memory devices, for example, a single, common external voltage supply may mask very different internal designs of the two different flash devices which otherwise might require multiple different and incompatible voltages in order to support each of the two suppliers of memory devices.
Unfortunately, power conversion circuits implemented on an integrated circuit are typically less efficient at converting energy from one voltage to another than a system-level circuit board implementation of a voltage conversion circuit. Among the factors contributing to lower efficiencies is the general commercial unfeasibility of rendering an inductor of sufficient value for use in a power conversion circuit. Inductive-based circuits are generally more efficient in power conversion than capacitive-based circuits. An additional factor is that capacitive features in an integrated circuit are relatively large, and must be minimized to allow, for example, for a maximum memory array size within the bounds of an integrated circuit.
FIG. 2A illustrates a charge pump circuit 200, as is conventionally employed on an integrated circuit to boost a voltage. Charge pump circuit 200 comprises diodes 241 through 245 and capacitive elements 251 through 254. Capacitive elements 251 through 254 are generally known as “pump capacitors.” Nodes 261 and 262 are known as “pump nodes.” A square wave clock signal, CKL1 220, is applied to or “drives” the bottom leg of capacitive element 251. The bottom leg of a capacitive element is generally known as a “pump driving node,” e.g., pump driving nodes 270 and 271. A supply voltage, Vcc 210 is applied at the anode of diode 241, and an output voltage is available at output node 260.
FIG. 2B illustrates the CLK1 220 and CLK2 230 signals. They typically range from 0 volts to Vcc 210, with a “high” duty cycle of, e.g., 25%. CLK2 230 has the same waveshape as CLK1 220, but is delayed by 180 degrees. Consequently, when CLK1 220 is high CLK2 230 is low and vice versa. In addition, there may be two periods of time when both signals are low.
Referring once again to FIG. 2A, when CLK1 220 is low, capacitive element 251 charges through diode 241: When capacitive element 251 is fully charged, node 261 will be at approximately Vcc. When capacitive element 251 is fully charged CLK1 220 transitions to a high level of approximately Vcc 210, and node 261 jumps to approximately 2 Vcc 210. Diode 241 is now reversed biased and does not conduct. CLK2 230 transitions to a low level, so diode 242 is forward biased and the voltage of node 261 is transferred to node 262, charging capacitive element 252.
When CLK2 230 subsequently transitions to a high level of approximately Vcc 210, node 262 jumps to approximately 3 Vcc 210. This process may be repeated throughout numerous stages to produce a range of output voltages for use by other circuits within an integrated circuit. Within the conventional art, diodes in a charge pump circuit have frequently been replaced by pass gate devices in order to eliminate a loss of energy due to a diode drop. It is to be appreciated that the use of pass gate devices requires additional clocking logic to open a pass gate when it is desirable to conduct, and to close a pass gate when it is desirable to block current flow.
Because flash memory devices have found widespread acceptance in low power applications, e.g., battery-powered cell phones and hand held computers, increasing the efficiency of internal power conversion circuitry within a flash memory device will beneficially reduce power consumption at the product level, thereby increasing battery life and making the product commercially more attractive. Consequently, improvements in integrated circuit power conversion circuit design are highly desirable and offer a competitive advantage over products containing less efficient designs.
Semiconductor processing equipment is extremely expensive. Fundamental semiconductor processing steps, e.g., implantation and diffusion, typically require long periods of development and extensive qualification testing. Implementing a new fabrication process requires considerable resources on the part of the semiconductor manufacturer. A manufacturer may have to alter or entirely revamp process libraries and process flows in order to implement a new fabrication process. Additionally, re-tooling a fabrication line is very expensive, both in terms of direct expenses as well as in terms of opportunity cost due to the time required to perform the re-tooling. Consequently, any solution to increase the rate of flash programming should be compatible with existing semiconductor processes and equipment without the need for revamping well established tools and techniques.
Accordingly, a need exists to increase the efficient of a charge pump. A further need exists for increasing the efficiency of a charge pump in a manner that is compatible and complimentary with conventional approaches to implementing high efficiency charge pumps. A still further need exists for the above mentioned needs to be achieved with existing semiconductor processes and equipment without revamping well established tools and techniques.